FIG. 1 is a conventional embedded power metal-oxide-semiconductor field effect transistor (power MOSFET) (for example NXP Corp. MOSFET), wherein both sides of a power MOSFET 11 include electroplated metal coatings (an upper metal coating 12 and a lower metal coating 13) respectively. A drain electrode 121, a gate electrode 122 and a source electrode 123 are separately arranged in the upper metal coating 12, wherein the gate electrode 122 and the source electrode 123 at the upper metal coating 12 are electrical connected with a top gate and a top source of the power MOSFET respectively. However, the drain electrode 121 at the upper metal is electrically connected with the lower metal coating 13. The bottom drain of the power MOSFET is electrically connected to the drain electrode 121 at the upper metal coating 12 via the electrical connection between the upper metal coating 12 and the lower metal coating 13, so that the drain, the gate and the source electrodes of the power MOSFET device are arranged on the top side of the device. As such, the chip package is thinner. In the conventional embedded power MOSFET chip shown in FIG. 1, the MOSFET chip 11 is 150 μm thick and is attached, via a conductive bonding material such as tin solder, on the metal coating 13 of 36 μm thick, therefore the whole package thickness is 200 μm with a size of 3.2 mm×3.2 mm.
FIG. 2 is another conventional multi-chip power MOSFET package (for example AOS Corp. MOSFET package) including a lead frame 21, a clip 22 and semiconductor chips 23, 24, 25. Semiconductor chip 24 and semiconductor chip 25 are attached on the lead frame 21 and the metal clip 22 is then attached on top of chips 24 and 25. A semiconductor chip 23 is mounted on the clip 22. The clip 22 and the lead frame 21 are electrically connected together. The semiconductor chip 25 is a pre-molded chip with a thickness of 100 μm. The semiconductor chip 24 and the semiconductor chip 25 are connected to each other through the metal clip 22. The semiconductor chip 23 is an integrated circuit (IC) chip, which is connected with a pin of the lead frame 21 through a bonding wire. The whole package thickness is 1.1 mm and its size is 3.5 mm×5 mm.
Although the conventional package as shown in FIG. 1 has the advantages of achieving flexible package design and the extremely thin package process and easy implementation in a system in package (SIP), its thermal performance and electrical performance for high-power device are not good, for example the resistance of the device is 7-8 milliohm. The conventional package as shown in FIG. 2 has better electrical performance and thermal performance, thinner die package with the pre-molded chip compared with the one shown in FIG. 1, and compatibility with the traditional package process. However, this process is unable to achieve a thin package due to the loop height of the wire bond (WB) and the stacked structure and is difficult to implement in the SIP. In addition, this process cannot achieve the flexible package design due to the wire bonding limitation. The high difficulty, low package yield and inflexibility of this process are caused of wire bonding issue after solder flux cleaning process, mold flash issue caused by the complex structure of the lead frame and the deformation in the high-temperature package process. Finally, this process is high cost due to the expensive gold bonding wire for interconnection of the power chip and the logic IC chip.